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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order Number: MC100ES8223/D Rev 0, 11/2001
Preliminary Information
Low Voltage 1:22 Differential HSTL Clock Fanout Buffer
The Motorola MC100ES8223 is a bipolar monolithic differential clock fanout buffer. Designed for the most demanding clock distribution systems, the MC100ES8223 supports various applications that require the distribution of precisely aligned differential clock signals. Using SiGe technology and a fully differential architecture, the device offers very low skew outputs and superior digital signal characteristics. Target applications for this clock driver are high performance clock distribution in computing, networking and telecommunication systems. Features * 1:22 differential clock fanout buffer * 50 ps maximum device skew1
MC100ES8223
LOW-VOLTAGE 1:22 DIFFERENTIAL HSTL CLOCK FANOUT DRIVER
* * * * * *
SiGe technology Supports DC to 800 MHz operation1 of clock or data signals 1.5V HSTL compatible differential clock outputs PECL and HSTL compatible differential clock inputs 3.3V power supply for device core, 1.5V or 1.8V HSTL output supply Standard 64 lead LQFP package with exposed pad for enhanced thermal characteristics
TC SUFFIX 64-LEAD LQFP PACKAGE EXPOSED PAD CASE 840K
* Supports industrial temperature range * Pin and function compatible to the MC100EP223
Functional Description The MC100ES8223 is designed for low skew clock distribution systems and supports clock frequencies up to 800 MHz1. The device accepts two clock sources. The HCLK input can be driven by HSTL compatible signals, the PCLK input accepts PECL compatible signals. The selected input signal is distributed to 22 identical, differential HSTL outputs. In order to meet the tight skew specification of the device, both outputs of a differential output pair should be terminated, even if only one output is used. In the case where not all 22 outputs are used, the output pairs on the same package side as the parts being used on that side should be terminated. The HSTL compatible output levels are generated with an open emitter architecture. This minimizes part-to-part and output-to-output skew. The open-emitter outputs require a 50 DC termination to GND (0V). The output supply voltage can be either 1.5V or 1.8V, the core voltage supply is 3.3V. The output enable (OE) is synchronous so that the outputs will only be enabled/disabled when they are already in the LOW state. In the case of an asynchronous control, there is a chance of generating a `runt' clock pulse when the device is enabled/disabled. The MC100ES8223 is pin and function compatible to the MC100EP223.
1. AC specifications are design targets and subject to change
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.
(c) Motorola, Inc. 2001
MC100ES8223
VCCO Q7 Q7 Q8 Q8 Q9 Q9 Q10 Q10 Q11 Q11 Q12 Q12 Q13 Q13 VCCO
Q0 Q0
VCC
HCLK HCLK 0 1

Q1 Q1 Q2 Q2 Q3 Q3

VCC
OE
PCLK PCLK
Q18 Q18 Q19 Q19
CLK_SEL
VCC
Q20 Q20 Q21 Q21
VCCO Q6 Q6 Q5 Q5 Q4 Q4 Q3 Q3 Q2 Q2 Q1 Q1 Q0 Q0 VCCO
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 49 32 50 31 51 30 52 29 53 28 54 27 55 26 56 25 MC100ES8223 57 24 58 23 59 22 60 21 61 20 62 19 63 18 64 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 VCCO NC NC VCC HSTL HSTL CLK_SEL PCLK Q21 Q21 VCCO PCLK GND OE NC NC
VCCO Q14 Q14 Q15 Q15 Q16 Q16 Q17 Q17 Q18 Q18 Q19 Q19 Q20 Q20 VCCO
OE
Figure 1. MC100ES8223 Logic Diagram Table 1. Pin Configuration
Pin HCLK1, HCLK PCLK, PCLK0 CLK_SEL OE Q[0-21], Q[0-21] GND VCC VCCO I/O Input Input Input Input Output Supply Supply Supply Type HSTL PECL LVCMOS LVCMOS HSTL
Figure 2. 64-Lead Package Pinout (Top View)
Function Differential HSTL reference clock signal input Differential PECL reference clock signal input Reference clock input select Output enable/disable. OE is synchronous to the input reference clock which eliminates possible output runt pulses when the OE state is changed. Differential clock outputs Negative power supply Positive power supply of the device core (3.3V) Positive power supply of the HSTL outputs. All VCCO pins must be connected to the positive power supply (1.5V or 1.8V) for correct DC and AC operation.
Table 2. Function Table
Pin CLK_SEL OE 0 HCLK, HCLK input pair is the reference clock. HCLK is HSTL compatible. Outputs disabled, Q[0:21]=L, Q[0:21]=H 1 PCLK, PCLK input pair is the reference clock. PCLK is PECL compatible. Outputs enabled
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TIMING SOLUTIONS
MC100ES8223
Table 3. Absolute Maximum Ratingsa
Symbol VCC VCCO VIN VOUT IIN IOUT TS Supply Voltage Supply Voltage DC Input Voltage DC Output Voltage DC Input Current DC Output Current Storage temperature -65 Characteristics Min -0.3 -0.3 -0.3 -0.3 Max 3.6 3.6 VCC + 0.3 VCC + 0.3 20 50 125 Unit V V V V mA mA C Condition
a. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied.
Table 4. General Specifications
Symbol VTT MM HBM CDM LU CIN JA, JB, JC TJ a. Characteristics Output termination voltage ESD Protection (Machine model) ESD Protection (Human body model) ESD Protection (Charged device model) Latch-up immunity Input Capacitance Thermal resistance (junction-to-ambient, junction-to-board, junction-to-case) Operating junction temperaturea (continuous operation) MTBF = 9.1 years 200 2000 TBD 200 4.0 See Table 7 "Thermal Resistance" on page 6 Min Typ 0 Max Unit V V V V mA pF C/W Inputs Condition
0
110
C
Operating junction temperature impacts device life time. Maximum continuous operating junction temperature should be selected according to the application life time requirements (See application note AN1545 for more information). The device AC and DC parameters are specified up to 110C junction temperature allowing the MC100ES8223 to be used in applications requiring industrial temperature range. It is recommended that users of the MC100ES8223 employ thermal modeling analysis to assist in applying the junction temperature specifications to their particular application.
TIMING SOLUTIONS
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MOTOROLA
MC100ES8223
Table 5. DC Characteristics (VCC = 3.3V5%, VCCO = 1.5V0.1V or VCCO=1.8V0.1V, TJ = 0C to + 110C)a
Symbol Characteristics Min Typ Max Unit Condition Clock input pair HCLK, HCLK (HSTL differential signals) VDIF Differential input voltageb VX, IN VIH VIL IIN Differential cross point voltagec Input high voltage Input low voltage Input Current
0.2 0.68 VX+0.1 VX-0.1 150 0.9
V V V V A VIN = VX 0.1V Differential operation Differential operation
Clock input pair PCLK, PCLK (PECL differential signals) VPP Differential input voltaged VCMR VIH VIL IIN VIL VIH IIN VX, OUT VOH VOL ICC ICCOf a. b. c. d. e. f. Differential cross point voltagee Input voltage high Input voltage low Input Currenta
0.15 1.0 VCC-1.165 VCC-1.810
1.0 VCC-0.6 VCC-0.880 VCC-1.475 150
V V V V A
VIN = VIH or VIN
LVCMOS control inputs OE, CLK_SEL Input voltage low Input voltage high Input Current 2.0 150 0.8 V V A VIN = VIH or VIN
HSTL clock outputs (Q[0-21], Q[0-21]) Output differential crosspoint Output High Voltage Output Low Voltage 0.68 1.1 0.4 0.75 0.9 V V V
Supply current Maximum Quiescent Supply Current without output termination current Maximum Quiescent Supply Current, outputs terminated 50W to VTT TBD TBD TBD TBD mA mA VCC pin (core) VCCO pins (outputs)
DC characteristics are design targets and pending characterization. VDIF (DC) is the minimum differential HSTL input voltage swing required for device functionality. VX (DC) is the crosspoint of the differential HSTL input signal. Functional operation is obtained when the crosspoint is within the VX (DC) range and the input swing lies within the VPP (DC) specification. VPP (DC) is the minimum differential input voltage swing required to maintain device functionality. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR (DC) range and the input swing lies within the VPP (DC) specification. ICC includes current through the output resistors (all outputs terminated to VTT).
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TIMING SOLUTIONS
MC100ES8223
Table 6. AC Characteristics (VCC = 3.3V5%, VCCO = 1.5V0.1V or VCCO = 1.8V0.1V, TJ = 0C to + 110C)a b
Symbol Characteristics Min Typ Max Unit Condition Clock input pair HCLK, HCLK (HSTL differential signals) VDIF Differential input voltagec (peak-to-peak) VX, IN fCLK tPD Differential cross point voltaged Input Frequency Propagation Delay HCLK0 to Q[0-21]
0.4 0.68 0-800 0.9 TBD TBD
V V MHz ps
Clock input pair PCLK, PCLK (PECL differential signals) VPP Differential input voltagee (peak-to-peak) VCMR fCLK tPD VX, OUT VOH VOL VO(P-P) tsk(O) tsk(PP) tJIT(CC) DCO a. b. c. d. e. f. Differential input crosspoint voltagef Input Frequency Propagation Delay PCLK0 to Q[0-21]
0.2 1 0-800
1.0 VCC-0.6 TBD
V V MHz ps Differential Differential
HSTL clock outputs (Q[0-21], Q[0-21]) Output differential crosspoint Output High Voltage Output Low Voltage Differential output voltage (peak-to-peak) Output-to-output skew Output-to-output skew (part-to-part) Output cycle-to-cycle jitter Output duty cycle TBD 50 0.5 50 TBD TBD TBD % DCfref= 50% 0.68 1 0.5 0.75 0.9 V V V V ps ps Differential Differential
tr, tf Output Rise/Fall Time 0.05 TBD ns 20% to 80% DC characteristics are design targets and pending characterization. AC characteristics apply for parallel output termination of 50 to VTT. VDIF (DC) is the minimum differential HSTL input voltage swing required for device functionality. VX (DC) is the crosspoint of the differential HSTL input signal. Functional operation is obtained when the crosspoint is within the VX (DC) range and the input swing lies within the VDIF (DC) specification. VPP (AC) is the minimum differential PECL input voltage swing required to maintain AC characteristics including tpd and device-to-device skew. VCMR (AC) is the crosspoint of the differential HSTL input signal. Normal AC operation is obtained when the crosspoint is within the VCMR (AC) range and the input swing lies within the VPP (AC) specification. Violation of VCMR (AC) or VPP (AC) impacts the device propagation delay, device and part-to-part skew. ZO = 50 ZO = 50
Differential Pulse Generator Z = 50W
RT = 50 VTT
DUT MC100ES8223
RT = 50 VTT
Figure 3. MC100ES8223 AC test reference
HCLK HCLK Q[0-21] Q[0-21] tPD (HCLK to Q[0-21]) VDIF=1.0V PCLK VX=0.75V PCLK Q[0-21] Q[0-21] tPD (PCLK to Q[0-21]) VPP=0.8V
VCMR=VCC-1.3V
Figure 4. MC100ES8223 AC reference measurement waveform
Figure 5. MC100ES8223 AC reference measurement waveform
TIMING SOLUTIONS
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MC100ES8223
APPLICATIONS INFORMATION
Using the thermally enhanced package of the MC100ES8223 The MC100ES8223 uses a thermally enhanced exposed pad (EP) 64 lead LQFP package. The package is molded so that the leadframe is exposed at the surface of the package bottom side. The exposed metal pad will provide the low thermal impedance that supports the power consumption of the MC100ES8223 high-speed bipolar integrated circuit and eases the power management task for the system design. A thermal land pattern on the printed circuit board and thermal vias are recommended in order to take advantage of the enhanced thermal capabilities of the MC100ES8223. Direct soldering of the exposed pad to the thermal land will provide an efficient thermal path. In multilayer board designs, thermal vias thermally connect the exposed pad to internal copper planes. Number of vias, spacing, via diameters and land pattern design depend on the application and the amount of heat to be removed from the package. A nine thermal via array, arranged in a 3 x 3 array and using a 1.2 mm pitch in the center of the thermal land is the absolute minimum requirement for MC100ES8223 applications on multi-layer boards. The recommended thermal land design comprises a 5 x 5 t h e r m a l v i a a r r a y a s s h o w n i n F i g u r e 6. "Recommended thermal land pattern", providing an efficient heat removal path.
all units mm
recommended 5 x 5 thermal via array. Because a large solder mask opening may result in a poor release, the opening should be subdivided as shown in Figure 7. For the nominal package standoff 0.1 mm, a stencil thickness of 5 to 8 mils should be considered.
all units mm
Thermal via array (5x5), 1.2 mm pitch, 0.3 mm diameter
Figure 7. Recommended solder mask openings For thermal system analysis and junction temperature calculation the thermal resistance parameters of the package is provided. For thermal system analysis and junction temperature calculation the thermal resistance parameters of the package is provided: Table 7. Thermal Resistancea
ConvectionLFPM Natural 100 200 400 800 RTHJAb C/W 57.1 50.0 46.9 43.4 38.6 RTHJAc C/W 24.9 21.3 20.0 18.7 16.9 15.8 9.7 RTHJCd C/W RTHJBe C/W
7
7
Thermal via array (5x5), 1.2 mm pitch, 0.3 mm diameter
Exposed pad land pattern
Figure 6. Recommended thermal land pattern The via diameter is should be approx. 0.3 mm with 1 oz. copper via barrel plating. Solder wicking inside the via resulting in voids during the solder process must be avoided. If the copper plating does not plug the vias, stencil print solder paste onto the printed circuit pad. This will supply enough solder paste to fill those vias and not starve the solder joints. The attachment process for exposed pad package is equivalent to standard surface mount packages. Figure 7. "Recommended solder mask openings" shows a recommend solder mask opening with respect to the
a. Thermal data pattern with a 3 x 3 thermal via array on 2S2P boards (based on empirical results) b. Junction to ambient, single layer test board, per JESD51-6 c. Junction to ambient, four conductor layer test board (2S2P), per JES51-6 d. Junction to case, per MIL-SPEC 883E, method 1012.1 e. Junction to board, four conductor layer test board (2S2P) per JESD 51-8 It is recommended that users employ thermal modeling analysis to assist in applying the general recommendations to their particular application. The exposed pad of the MC100ES8223 package does not have an electrical low impedance path to the substrate of the integrated circuit and its terminals. The thermal land should be connected to GND through connection of internal board layers.
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I II IIIIIIIII IIIIIIIII IIII IIIIII I IIIIIIIIII IIIIIIIIII IIIIIIII II IIII II IIIIIIIIII II II IIII II IIIIIIIIII IIII IIII IIIIIIIIII IIIIIIIIII IIII IIII IIIIIIIIII IIIIIIIIII IIII IIIIIIIIII II IIII IIIIIIIIII IIIIII I I IIIIIIIIII IIIIIIIIII IIIIIIIII IIIIIIIII IIIIIIIII III I I
0.2 1.0 0.2 7 1.0
7
Exposed pad land pattern
I IIIII IIIIIIIIII IIIIIIIIII I IIIII IIIIIIIIII IIIIIIII I IIIIIIIIII I I IIIIIIII I II II IIIIIIII I II II I I II II IIIIIIII I I I II IIIIIIII I II II II IIIIIIIII IIIIII I IIIIIIIIII IIIIIIIIII IIIIIIIII IIIII IIIII
TIMING SOLUTIONS
MC100ES8223
OUTLINE DIMENSIONS
TC SUFFIX PLASTIC LQFP PACKAGE, EXPOSED PAD CASE 840K-01 ISSUE O
4X 4X 16 TIPS
0.2 H A-B D D
PIN 1 IDENTIFIER 1 64 49 48
0.2 C A-B D
A2 0.05
S
(S) Z1 Z R 0.25
GAGE PLANE
A
B E1 E A1 R1 L (L1)
3X
VIEW Y
16 17 32 33
E1/2
VIEW AA E/2
NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M-1994. 3. DATUMS A, B AND D TO BE DETERMINED AT DATUM PLANE H. 4. DIMENSIONS D AND E TO BE DETERMINED AT SEATING PLANE C. 5. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED THE MAXIMUM b DIMENSION BY MORE THAN 0.08 mm. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSION AND ADJACENT LEAD OR PROTRUSION 0.07 mm. 6. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 mm PER SIDE. D1 AND E1 ARE MAXIMUM PLASTIC BODY SIZE DIMENSIONS INCLUDING MOLD MISMATCH. 7. EXACT SHAPE OF EACH CORNER IS OPTIONAL. 8. THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.10 mm AND 0.25 mm FROM THE LEAD TIP. DIM A A1 A2 b b1 c c1 D D1 e E E1 L L1 R1 R2 S F G Z Z1 Z2 Z3 MILLIMETERS MIN MAX --- 1.60 0.05 0.15 1.35 1.45 0.17 0.27 0.17 0.23 0.09 0.20 0.09 0.16 12.00 BSC 10.00 BSC 0.50 BSC 12.00 BSC 10.00 BSC 0.45 0.75 1.00 REF 0.08 --- 0.08 --- 0.20 --- 6.00 7.00 6.00 7.00 0_ 7_ 0_ --- 11 _ 13 _ 11 _ 13 _
D1/2 D/2 D1 D H A
4X
Z2 0.08 C
J C
SEATING PLANE
64X
b
4X
Z3 VIEW AA
J
0.08
M
C A-B D X
X=A, B OR D
C L AB AB
BASE METAL
e/2
60X
e
F
VIEW Y
8 b1
8
c
PLATING
ROTATED 90 _ CLOCKWISE
TIMING SOLUTIONS
EEEEE CCCC EEEEE CCCC EEEEE CCCC
8 b SECTION AB-AB
c1 8
G
EXPOSED PAD
VIEW J-J
7
MOTOROLA
MC100ES8223
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. MOTOROLA and the logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners.
E Motorola, Inc. 2001.
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MC100ES8223/D TIMING SOLUTIONS

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